EVMDD-based analysis and diagnosis methods of multi-state systems with multi-state components

A multi-state system with multi-state components is a model of systems, where performance, capacity, or reliability levels of the systems are represented as states. It usually has more than two states, and thus can be considered as a multi-valued function, called a structure function. Since many structure functions are monotone increasing, their multi-state systems can be represented compactly by edge-valued multi-valued decision diagrams (EVMDDs). This paper presents an analysis method of multi-state systems with multi-state components using EVMDDs. Experimental results show that, by using EVMDDs, structure functions can be represented more compactly than existing methods using ordinary MDDs. Further, EVMDDs yield comparable computation time for system analysis. This paper also proposes a new diagnosis method using EVMDDs, and shows that the proposed method can infer the most probable causes for system failures more efficiently than conventional methods based on Bayesian networks.Japan Society for the Promotion of ScienceMinistry of Education, Culture, Sports, Science and Technology (MEXT)Hiroshima City UniversityGrant-in Aid No. 2500050 (MEXT)Grant no. 0206 (HCU)Grant in Aid for Scientific Research (JSPS

Minimization of average path length in BDDs by variable reordering

12th International Workshop on Logic and Synthesis, Laguna Beach, California, USA, May 28-30, 2003, pp.207-213.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Minimizing the Average Path Length (APL) in a BDD reduces the time needed to evaluate Boolean functions represented by BDDs. This paper describes an efficient heuristic APL minimization procedure based on BDD variable reordering. The reordering algorithm is similar to classical variable sifting with the cost function equal to the APL rather than the number of BDD nodes. The main contribution of our paper is a fast way of updating the APL during the swap of two adjacent variables. Experimental results show that the proposed algorithm effectively minimizing the APL of large MCNC benchmark functions, achieving reductions of up to 47%. For some benchmarks, minimizing APL also reduces the BDD node count

EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components *

A multi-state system with multi-state components is a model of systems, where performance, capacity, or reliability levels of the systems are represented as states. It usually has more than two states, and thus can be considered as a multi-valued function, called a structure function. Since many structure functions are monotone increasing, their multi-state systems can be represented compactly by edge-valued multivalued decision diagrams (EVMDDs). This paper presents an analysis method of multi-state systems with multi-state components using EVMDDs. Experimental results show that, by using EVMDDs, structure functions can be represented more compactly than existing methods using ordinary MDDs. Further, EVMDDs yield comparable computation time for system analysis. This paper also proposes a new diagnosis method using EVMDDs, and shows that the proposed method can infer the most probable causes for system failures more efficiently than conventional methods based on Bayesian networks

多値決定グラフを用いた論理関数の表現法と評価法

九州工業大学博士学位論文　学位記番号:情工博甲第146号　学位授与年月日:平成16年9月30

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

Design method of numerical function generators based on polynomial approximation for FPGA implementatio

Programmable numerical function generators: Architectures and synthesis system

FPL2005, Tampere, Aug.24-26, 2005, pp.118-123.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (Look-Up Table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (Field-Programmable Gate Array). Experimental results show the efficiency of our architecture and synthesis system

Programmable numerical function generators based on quadratic approximation: Architecture and synthesis method

ASPDAC 2006, Yokohama Jan. 2006, pp. 378-383.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper presents an arhitecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Implementation results on an FPGA show that: 1) our NFGs require only 4% of the memory needed by NFGs based on the 5th-order approximation with uniform segmentation. Our automatic synthesis system generates such compact NFGs quickly

Systematic design method for two-variable numeric function generators using multiple-valued decision diagrams

IEICE Transactions on Information and Systems, Vol. E93-D No. 8 pp. 2059-2067, Aug. 2010.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD..

Design method of numerical function generators based on polynomial approximation for FPGA implementation

DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, Aug. 27 - 31, 2007, Lubeck, Germany, pp. 280-287.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper focuses on numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces signicantly the NFG's memory size. However, larger k requires more logic elements and multipliers.numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces signicantly the NFG's memory size. However, larger k requires more logic elements and multipliers. To quantify this tradeoff, we introduce the FPGA utilization measure, and then determine the optimum polynomial order k. Experimental results show that: 1) for low accuracies (up to 17 bits), 1st order polynomial approximations produce the most efficient implementations; and 2) for higher accuracies (18 to 24 bits), 2nd-order polynomial approximations produce the most efficient implementations